Innovative Heterogeneous Design of Low Power Reconfigurable Router for Network on Chip (NOC)

In this paper, objective is to first characterize the need of a heterogeneous reconfigurable router and show how an NoC built with reconfigurable routers allows the use of buffers with smaller depths. These in turn have a similar performance w.r.t. an NoC using a fixed size router, the latter showing a large buffer depth and incurring lower efficiency than the design presented here which can also lead to higher power consumption than the project design. Considering the NoC components, as crossbars, arbiters, buffers, and links, in the experiments realized by [4] the buffers were the largest leakage power consumers, dissipating approximately 64% of the whole power budget. In this way, the buffers can be considered as candidates for leakage power optimization by handling the buffers efficiently and effectively, since even at high loads, there can be 85% of idle buffers [4]. Regarding dynamic power, the buffers’ consumption is also high, and it increases rapidly as the packet flow throughput increases [5]. Therefore, this paper particular goal is to provide an NoC router with a certain amount of heterogeneous reconfiguration logic, allowing changes in the amount of buffer utilization in each input channel, in conformity with the communication needs. The principle is that each input channel can lend/borrow buffer units to/from neighbouring channels in order to obtain a determined bandwidth. When a channel does not need its entire available buffer, it can lend buffer word slots to neighbouring channels. The inefficiency in the amount of buffers used within a homogeneous router, and the gains that can be achieved using the proposed strategy can be shown at further level. The focus is on providing a reconfigurable router that can be tested to optimize power and improve energy usage while sustaining high performance, even when the application changes the communication pattern.